U.S. patent application Ser. No. 10/294,317 filed Nov. 14, 2002 entitled “Method and Apparatus for Performing Multiport Thru-Reflect-Line Calibration and Measurement” (herein “the '317 Patent Application”) teaches a method and apparatus for performing a thru-reflect-line calibration with a multiple port vector network analyzer (“VNA”). The disclosed method teaches determination of ten-term error coefficients that may be used in a method disclosed in U.S. Pat. No. 5,434,511 (herein “the '511 Patent”) to arrive at S-parameters of a device under test (herein “the DUT”) with systematic errors attributable to the VNA and the multiport test set corrected out of the measured S-parameters of the DUT. In the method according to the '317 Patent Application, it is necessary to know a type of high reflect calibration standard used in the process. Also, in the method disclosed in the '317 Patent Application, if the thru calibration standard used in the calibration procedure is a non-zero thru, then its electrical length must be known and specified by the calibration standard manufacturer in order to fully characterize the error coefficients in the calibration process. In many cases, the electrical length of the non-zero thru is either unknown, not known to a sufficient accuracy, or is a non-repeatable value. A thru calibration standard is typically unknown for on-wafer calibrations because the landing of the probe to the calibration standard is non-repeatable, which renders the electrical length also non-repeatable, and therefore, unpredictable. Even though manufacturers of coaxial calibration standards often include electrical length data, over time and after multiple uses, the electrical length can change making a calibration process that relies on the electrical length specifications, less accurate. Due to machining, process, and other non-repeatable manufacturer variations, the manufacturer specifications of the thru calibration standards may not be as accurate as the calibration and measurement presumes. In addition, frequent use of the calibration standard can cause the dimensions and, therefore, the calibration specifications to change over time while the calibration process presumes otherwise. In high frequency on-wafer measurements, a non-zero thru is used exclusively. Furthermore, in an on-wafer calibration process, it is difficult to land probes repeatably on a calibration substrate to coincide with the electrical delay value provided by the calibration standard manufacturer. Any discrepancy between the actual electrical delay and the presumed electrical delay causes uncertainties in the calibration and, therefore, the corrections made to the measurement of a device under test (“DUT”). The uncertainties are exacerbated as measurement frequencies increase.
There is a need, therefore, to improve the thru-reflect-line calibration process to accommodate a thru calibration standard with an unknown delay or an unknown type of high reflect calibration standard with a known phase offset.